Type of Document Master's Thesis Author TASKIN, BARIS URN etd-04182003-153835 Title Linearization of The Timing Analysis and Optimization of Level-Sensitive Circuits Degree Master of Science in Electrical Engineering Program Electrical Engineering School School of Engineering Advisory Committee
Advisor Name Title Ivan S. Kourtev Committee Chair Marlin H. Mickle Committee Member Steven P. Levitan Committee Member Keywords
- Linear Programming
- Digital synchronous VLSI circuits
- Static Timing Analysis
- Optimization
Date of Defense 2003-03-28 Availability unrestricted Abstract This thesis describes a linear programming (LP) formulation applicable to the static timing analysis of large scale synchronous circuits with level-sensitive latches. The automatic timing analysis procedure presented here is composed of deriving the connectivity information, constructing the LP model and solving the clock period minimization problem of synchronous digital VLSI circuits. In synchronous circuits with level-sensitive latches, operation at a reduced clock period (higher clock frequency) is possible by takingadvantage of both non-zero clock skew scheduling
and time borrowing. Clock skew scheduling
is performed in order to exploit the benefits of nonidentical clock signal delays on circuit timing. The time borrowing property of level-sensitive circuits permits higher operating frequencies compared to edge-sensitive
circuits. Considering time borrowing in the timing analysis, however, introduces non-linearity in this timing analysis. The modified big M (MBM) method is defined in order to transform the non-linear constraints arising in the problem formulation into solvable linear constraints. Equivalent LP model problems
for single-phase clock synchronization of the ISCAS’89 benchmark circuits are generated and these problems are solved by the industrial LP solver CPLEX. Through the simultaneous application of time borrowing and clock skew scheduling, up to 63% improvements are demonstrated in minimum clock period with respect to zero-skew edge-sensitive synchronous circuits. The timing constraints governing the
level-sensitive synchronous circuit operation not only solve the clock period minimization problem but also provide a common framework for the general timing analysis of such circuits. The inclusion of additional constraints into the problem formulation in order to meet the timing requirements imposed by specific application
environments is discussed.
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