Type of Document Dissertation Author Taskin, Baris Author's Email Address taskin@coe.drexel.edu URN etd-07152005-141653 Title Advanced Timing and Synchronization Methodologies for Digital VLSI Integrated Circuits Degree Doctor of Philosophy Program Electrical Engineering School School of Engineering Advisory Committee
Advisor Name Title Prof. Ivan S. Kourtev Committee Chair Prof. Alex K. Jones Committee Member Prof. Brady Hunsaker Committee Member Prof. Marlin H. Mickle Committee Member Prof. Steven P. Levitan Committee Member Keywords
- Synchronization
- Time Borrowing
- Resonant Clocking
- Linear Programming
- Level-Sensitive Circuits
- Timing
- Clock Skew Scheduling
Date of Defense 2005-07-06 Availability unrestricted Abstract This dissertation addresses timing and synchronization methodologies that are critical to the design, analysis and optimization of high-performance, integrated digital VLSI systems. As process sizes shrink and design complexities increase, achieving timing closure for digital VLSI circuits becomes a significant bottleneck in the integrated circuit design flow. Circuit designers are motivated to investigate and employ alternative methods to satisfy the timing and physical design performance targets. Such novel methods for the timing and synchronization of complex circuitry are developed in this dissertation and analyzed for performance and applicability.
Mainstream integrated circuit design flow is normally tuned for zero clock skew, edge-triggered circuit design. Non-zero clock skew or multi-phase clock synchronization is seldom used because the lack of design automation tools increases the length and cost of the design cycle. For similar reasons, level-sensitive registers have not become an industry standard despite their superior size, speed and power consumption characteristics compared to conventional edge-triggered flip-flops.
In this dissertation, novel design and analysis techniques that fully automate the design and analysis of non-zero clock skew circuits are presented. Clock skew scheduling of both edge-triggered and level-sensitive circuits are investigated in order to exploit maximum circuit performances. The effects of multi-phase clocking on non-zero clock skew, level-sensitive circuits are investigated leading to advanced synchronization methodologies. Improvements in the scalability of the computational timing analysis process with clock skew scheduling are explored through partitioning and parallelization.
The integration of the proposed design and analysis methods to the physical design flow of integrated circuits synchronized with a next-generation clocking technology-resonant rotary clocking technology-is also presented. Based on the design and analysis methods presented in this dissertation, a computer-aided design tool for the design of rotary clock synchronized integrated circuits is developed.
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