| Type of Document |
Master's Thesis |
| Author |
Kusic, Dara Marie
|
| URN |
etd-07172005-165922 |
| Title |
A Hybrid Hardware/Software Architecture That Combines a 4-wide Very Long Instruction Word Software Processor (VLIW) with Application-specific Super-complex Instruction Set Hardware Functions |
| Degree |
Master of Science in Electrical Engineering |
| Program |
Electrical Engineering |
| School |
School of Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Raymond R. Hoare |
Committee Chair |
| Alex K. Jones |
Committee Member |
| Steven P. Levitan |
Committee Member |
|
| Keywords |
- parallel architecture
- VLIW
- application speedup
- scaling effects
- co-processor
- hardware/software interface
- hybrid processor
- computer architecture
|
| Date of Defense |
2005-07-06 |
| Availability |
unrestricted |
Abstract
Application-driven processor designs are becoming increasingly feasible. Today, advances in field-programmable gate array (FPGA) technology are opening the doors to fast and highly-feasible hardware/software co-designed architectures. Over 100,000 FPGA logic array blocks and nearly 100 ASIC multiply-accumulate cores combine with extensible CPU cores to foster the design of configurable, application-driven hybrid processors.
This thesis proposes a hardware/software co-designed architecture targeted to an FPGA. The architecture is a very-long instruction-word (VLIW) processor coupled with super-complex instruction set (SuperCISC) hardware co-processors. Results of the VLIW/SuperCISC show performance speedups over a single-issue processor of 9x to 332x, and entire application speedups from 4x to 127x. Contributions of this research include a 4-way VLIW designed from the ground up, a zero-overhead implementation of a hardware/software interface, evaluation of the scalability of shared data stores, examples of application-specific hardware accelerants, a SystemC simulator, and an evaluation of shared memory configurations.
|
| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
dmk_thesis.pdf |
2.08 Mb |
00:09:36 |
00:04:56 |
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